Intel 64 and IA-32 | Atomic operations including acquire / release semantic

According to the Intel 64 and IA-32 Architectures Software Developer's Manual the LOCK Signal Prefix "ensures that the processor has exclusive use of any shared memory while the signal is asserted". That can be a in the form of a bus or cache lock.

But - and that's the reason I'm asking this question - it isn't clear to me, if this Prefix also provides any memory-barrier.

I'm developing with NASM in a multi-processor environment and need to implement atomic operations with optional acquire and/or release semantics.

So, do I need to use the MFENCE, SFENCE and LFENCE instructions or would this be redundant?