Verilog Always block using (*) symbol

I have a simple question regarding how to write an always block in a Verilog module.
If I have the following inputs in my Verilog module:

input        [31:0] PCplus4 ;       // Value of PC + 4
input        [31:0] A;          // Value A, i.e. RSbus (Use Forwarded Value)
input        [31:0] B;          // Value B, i.e. RTbus (Use Forwarded Value)
input        [31:0] IMM;            // Extended Immediate Value
input        [25:0] TARGET;         // Target Address for Jumps
input         [3:0] BR;         // Branch Selector Input

Is there any difference if I use

always @ (*)  

instead of

always @ (PCplus4  or A or B or IMM or TARGET or BR)  

Is this always @ (*) syntax valid for all versions of Verilog?